Renesas Electronics /R7FA6M1AD /GPT_ODC /GTDLYR2B

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Interpret as GTDLYR2B

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (others)DLY

DLY=others

Description

GTIOC2B Rising Output Delay Register

Fields

DLY

GTIOCnB Output Rising Edge Delay Setting

0 (00000): No delay on rising edges

0 (others): Delay of DLY/32 times the PCLKD period is applied.

Links

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